`timescale 1ns / 1ps
module sim_fulladd1b;
    reg cin,a,b;
    wire cout,s;
    full_add_1b sim1(cin,a,b,cout,s);
    initial
    begin
        cin=0;a=0;b=0;
        fork
            repeat(10) #5 cin=~cin;
            repeat(10) #10 a=~a;
            repeat(10) #15 b=~b;
        join
    end
endmodule
